The Challenges in Signal Integrity and Power Integrity to Meet
the Demands of Expanding and Evolving Compute Platforms
As compute platforms evolve from mainframes and desktops toward laptops, portable tablets, smartphones and AR/AV Devices and back to data centers (in the age of AI), the demands of signal integrity and power integrity (SI/PI) challenges have been growing and changing. The newer platforms require more complex and sometimes drastically different SI/PI analysis approaches to optimize the system performance that are specific to these platforms.
In this talk, I will start with a review of the key methods developed in the last three decades to accurately solve very complex SI/PI problems, that have now become indispensable tools in designing the most powerful compute and communication electronic systems all around us. These accomplishments have been possible with the use of techniques such as scattering parameters, recursive convolution, model order reduction, target impedance, statistical simulation etc.
Then, the SI/PI techniques were successfully used to solve the latest power distribution network challenges of current SoC chips from very low power to very large power with trillions of gates in the latest technology node as well as high-speed signaling challenges at the data rates beyond 224 Gbps were also examined. This will be followed by a brief introduction to the machine learning techniques, where the details of some of the most promising machine learning techniques applied to signal and power integrity problems are reviewed. These include machine learning techniques applied to model order reduction, target power impedance of power distribution of modern SoC, and design space exploration, to name a few.
