Global SIPI University

Keynote
SI and PI challenges for enterprise server design

In recent years, enterprise server deployment growth is exponential, fueled by AI acceleration, cloud-native computing, and heterogeneous workloads. These systems now demand extreme bandwidth densities and power delivery capabilities, often exceeding multi-terabit signaling and multi-kilowatt power envelopes. Such requirements place profound challenges in signal integrity (SI) and power integrity (PI) design. This keynote will examine the SI and PI challenges inherent to modern server design, with emphasis on high-speed interconnects, advanced packaging technologies, and power delivery networks. In particular, this talk will show how physical constraints such as board real estate, mechanical limits, and cost-performance trade-offs influence design decisions. It will include practical cases, highlighting co-design strategies, modeling techniques, and system-level optimization approaches. The goal is to foster a deeper understanding of how SI/PI methodologies evolve to meet the demands of next-generation computing infrastructure.

Introduction to SI & PI
Introduction to Signal Integrity and Power Integrity

This presentation will introduce the concepts of signal and power integrity, and the evolution, in the past two decades, of the challenges associated with the modeling, analysis, and design of high speed interconnects and high-current PDNs. An overview of the current trends based on the state of the art of the technology discussed in the following sessions will be given.

Signal Integrity I
Lumped vs. distributed discontinuities,
transmission line effects, crosstalk & losses

As data rates and edge speeds in modern electronic systems continue to rise, the distinction between lumped and distributed discontinuities becomes critical for accurate signal-integrity and electromagnetic-compatibility design. This presentation gives an overview of how geometric and material transitions within interconnects behave either as localized impedance discontinuities or as electrically long structures exhibiting full transmission-line effects. Key mechanisms — including reflections, standing waves, and frequency-dependent propagation — are discussed to illustrate when traditional lumped-element approximations break down. The study further examines how distributed coupling paths give rise to near-end and far-end crosstalk, emphasizing the impact of trace geometry, dielectric properties, and return-path configuration. Additionally, conductor and dielectric losses are discussed in the context of attenuation, phase distortion, and their influence on high-speed waveform integrity. By integrating these phenomena into a unified perspective, the presentation highlights practical design considerations for minimizing signal degradation and ensuring robust performance across high-frequency interconnects.

Signal Integrity II
3D modeling and simulation,
circuit modeling and simulation, equalization

3D electromagnetic modeling and simulation, circuit-level modeling and simulation, and equalization are foundational to modern electronic system design, particularly for high-speed and high-frequency applications. When applied in an integrated manner, these techniques enable accurate performance prediction, early identification of signal- and power-integrity challenges, and systematic design optimization prior to physical prototyping—significantly reducing development time, cost, and overall technical risk. This presentation will highlight the successful design of modern SoCs and ASICs for wearable devices and infrastructure systems supporting AI workloads. As these designs incorporate both in-package and external memories with high-speed I/O interfaces and therefore require comprehensive electromagnetic analysis and circuit-level simulation. The discussion will include detailed system-level modeling and analysis methodologies used to optimize end-to-end performance across the complete signal and power delivery paths.

Signal Integrity III
VNA Measurements in Signal Integrity

Signal integrity has become a critical aspect of modern high-speed digital design, today more than ever as data rates continue to rise and reliable transmission become essential. In this seminar, we will understand how VNAs are used to identify potential signal integrity issues and address them using tools and applications integrated in the network analyzer. First, we will cover the basics of VNA parameters and time domain analysis, which is necessary to gain the correct insights about my DUT. Then we will discuss the topic of de-embedding and see how it can help the designer make the correct choices when developing his PCB. We will end this presentation with a live demo of our VNA in action, including real measurements of transmission lines.

Application Perspective
SI and PI aware design of automotive interconnects

The necessity of further improved EMC/ESD/SIPI behavior and optimized PCB design is obvious, because high-complexity products with enhanced safety/security requirements need to be managed. Advanced PCB’s with BGA-IC packages, high-speed clock lines with rich spectral-content, high-frequency signals with sharp rise-times and high slew-rates, often require an increased number of stacked PCB layers. To benefit from leading-edge technology processes and functions, many IC’s require several voltage-rails and an optimized PDN, allowing reliable Inter-Chip connections along with proper communication between Electrical Control Units. This presentation provides an overview of most current challenges and gives an outlook how the complexity and the challenges can be managed, while meeting cost and time to market constraints under the harsh conditions of automotive applications.